Dynamic random access memories (DRAM) are commonly used in modern integrated circuits. DRAMs need to be periodically refreshed in order to keep the stored information from being lost. The refresh is typically performed by refresh circuits, namely periodically reading cells that involves using oscillators.
FIG. 1 illustrates a conventional oscillator circuit. In an initial stage, a MOS device M0 is off. A current source CS1 provides a current for charging a capacitor C1, causing an increase in voltage V1. When voltage V1 is higher than the trip point of inverter G0, the states of inverters G0 and G1 flip. MOS device M0 is thus turned on, and charge stored in capacitor C1 is discharged. The discharging causes the lowering of voltage V1, and eventually another flip of the states of inverters G0 and G1. The charging process then starts again. The repeated charging and discharging results in voltage V1 having a saw-tooth waveform, and output voltage Vout having a square waveform. Output voltage Vout can be used to refresh DRAMs.
One of the reasons causing the states stored in DRAMs to be lost is leakage current. For example, a typical DRAM cell may include a capacitor and a transistor, wherein the state is stored by charging or discharging the capacitor. Leakage currents, however, will cause the stored charges to leak away. The leakage current is related to temperature, and when the temperature increases, the leakage current also increases. Accordingly, the DRAMs need to be refreshed more frequently, hence higher refresh rates are required at higher temperatures.
Conventionally, to ensure the correct operation of DRAMs at high temperatures, the refresh rate is set to a high level so that at a high temperature, the refresh rate can still satisfy the increased demand of refreshing. The increased refresh rate, however, causes more power to be consumed. Higher-than-necessary refresh rates at low temperatures cause an undesired increase in power consumption. Therefore, the optimal design is that the oscillators are temperature dependent, which means oscillators need to provide high refresh rates at high temperatures and low refresh rates at low temperatures. In this way, the requirements of data integrity and power consumption are balanced.
FIG. 2 schematically illustrates the period of an oscillator as a function of temperature. The Y-axis (Tref) indicates the periods of cycles of the oscillator. A DRAM refresh oscillator should not perform in forbidden region 2 due to the long periods of refresh cycles, and hence the states stored in DRAMs may be lost before next refresh. The oscillator should also not perform in forbidden region 4 due to the over-refresh rate, and hence needless power consumption. Region 6 is the preferred work region for oscillators. It can be estimated from FIG. 2 that the optimal refresh rate at 125° C. may be about 6 to 8 times higher than the refresh rate at 25° C.
Conventionally, to implement temperature-dependent oscillators, temperatures are detected first and then used to operate a digital circuit, which generates refresh signals based upon the detected temperatures. The detected temperatures are typically divided into segments, and several refresh rates may be generated by the digital circuit, each corresponding to a segment of the temperature range. It is obvious that within a temperature segment, the refresh rate is not temperature dependent, and thus this approach is not optimal.
Therefore, what is needed in the art is a fully temperature-dependent oscillator.